MAX1002CAX+T【PDF 6/12 页】IC ADC 6BIT 60MSPS DUAL 36-SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录2007

2页 3页 4页 5页 [6页]7页 8页 9页 10页

MAX1002

Low-Power, 60Msps, Dual, 6-Bit ADC

_______________________________________________________________________________________

AC ELECTRICAL CHARACTERISTICS

(VCC, VCCO = +5V ±5%; TA = +25°C; unless otherwise noted.)

Note 1: Best straight-line linearity method.

Note 2: A typical application will AC couple the analog input to the DC bias level present at the analog inputs (typically 2.35V).

However, it is also possible to DC couple the analog input (using differential or single-ended drive) within this common-

mode input range (Figures 4, 5).

Note 3: PSSR is defined as the change in the mid-gain, full-scale range as a function of the variation in VCC supply voltage

(expressed in decibels).

Note 4: The current in the VCCO supply is a strong function of the capacitive loading on the digital outputs. To minimize supply

transients and achieve the best dynamic performance, reduce the capacitive loading effects by keeping line lengths on the

digital outputs to a minimum.

Note 5: Offset-correction compensation enabled, 0.22F at Q and I compensation inputs (Figures 2, 3).

Note 6: tPD and tSKEW are measured from the 1.4V level of the output clock, to the 1.4V level of either the rising or falling edge of a

data bit. tDCLK is measured from the 50% level of the clock overdrive signal on TNK+ to the 1.4V level of DCLK. The capac-

itive load on the outputs is 15pF.

Gain = GND, open, VCC

GAIN = open (mid gain),

VIN = 50MHz, -1dB below FS

GAIN = open (mid gain)

5.7

ENOBM

5.6

5.85

Effective Number of Bits

Gain = open (mid gain)

Gain = VCC (low gain)

Q channel

I channel

CONDITIONS

MHz

Analog Input -0.5dB Bandwidth

Msps

fMAX

Maximum Sample Rate

-55

XTLK

Gain = VCC (high gain)

Crosstalk Between ADCs

LSB

-0.5

0.5

OFF

Input Offset (Note 5)

-0.5

0.5

35.4

SINAD

Signal-to-Noise and Distortion

Ratio

Bits

5.85

ENOBL

5.8

ENOBH

(Note 5)

-0.2

±0.1

0.2

Amplitude Match Between

ADCs

LSB

-0.5

±0.25

0.5

OMM2

Offset Mismatch Between ADCs

(Note 6)

3.6

tSKEW

Data Valid Skew

7.1

tPD

DCLK to Data-Propagation

Delay

degrees

-2

±0.5

UNITS

MIN

TYP

MAX

SYMBOL

PARAMETER

Phase Match Between ADCs

TNK+ to DCLK (Note 6)

5.3

tDCLK

Input to DCLK Delay

5.5

tAP

Aperture Delay

clock

cycle

Pipeline Delay

DYNAMIC PERFORMANCE (GAIN = open; external 60MHz clock (Figure 7); VINI, VINIQ = 20MHz sine; amplitude -1dB below FS;

unless otherwise noted.)

TIMING CHARACTERISTICS (data outputs: RL = 1M, CL = 15pF, Figure 8)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式